Logic Design, computer science assignment help

Logic Design, computer science assignment help

Answer the question at the end of the lab. There are five questions in total.

1. Instead of using : out STD_LOGIC_VECTOR (7 downto 0) in line 231 of Figure 1, why buffer is used? Inspect, what happens if you change buffer to out.

2. How does hierarchical schematic capture and hierarchical structural VHDL design techniques help one manage the complexity of the design process?

3. Were there any differences in the simulations of the first schematic capture version and the structural VHDL versions of the adder/subtractor module? If so describe these differences. If not speculate on why they are identical.

4. Were there any differences in the simulations of the structural and behavioral VHDL versions of the subtractor/adder module? If so describe these differences. If not speculate on why they are identical.

5. Describe the design trade-offs associated with the structural and behavioral versions in terms of ease of design entry, ability to control the low level

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