Altera Quartus II Project 4-bit Synchronous Up-Down Counter

Altera Quartus II Project 4-bit Synchronous Up-Down Counter

The project involves using Altera Quartus® II CAD system and proceeding with the following requirements:

Design and simulation of a four-bit Up-Down counter; you will need to use Flip-Flops JK negative edge triggered 74112. The flip flops are available in .mf library. This flip flops come in Dual-Packages so all you need is two of them. Implementation with other class of devices, like 71LS161/163 will not be considered. You need to take into consideration the following: a) The simulations should use a clock of 25 MHzb) The snap shots should show a complete count (from 0000 to 1111 and another for a count from 1111 to 0000), and should show uses of Asynchronous Clear and Preset. (SEE Attached PDF for Project Counter examples)

Bonus points implementing with ALTERA boards DE2-115. (Please do this)

Each student will turn in a report with the results of their design and simulation of the circuits.(SEE Attached Project Guidelines Document for report details and all project requirements).

"You need a similar assignment done from scratch? Our qualified writers will help you with a guaranteed AI-free & plagiarism-free A+ quality paper, Confidentiality, Timely delivery & Livechat/phone Support.

Discount Code: CIPD30

Click ORDER NOW..